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1 of 29 061907 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds28ea00 is a digital thermometer with 9-bit (0.5 c) to 12-bit (1/16 c) resolution and alarm function with nonvolatile (nv), user-programmable upper and lower trigger points. each ds28ea00 has its unique 64-bit registration number that is factory- programmed into the chip. data is transferred serially through the 1-wire ? protocol, which requires only one data line and a ground for communication. the improved 1-wire front end with hysteresis and glitch filter enables the ds28ea00 to perform reliably in large 1-wire networks. unlike other 1-wire thermo- meters, the ds28ea00 has two additional pins to implement a sequence detect function. this feature allows the user to discover the registration numbers according to the physical device location in a chain, e.g., to measure the temperature in a storage tower at different height. if the sequence detect function is not needed, these pins can be used as general- purpose input or output. the ds28ea00 can derive the power for its operation directly from the data line (?parasite power?), eliminating the need for an external power supply. applications data communication equipment process temperature monitoring hvac systems typical operating circuit v dd 1-wire master px. y (micro- controller) #1 #2 #3 v dd io ds28ea00 piob pioa gnd v dd io ds28ea00 piob pioa gnd v dd io ds28ea00 piob pioa gnd schematic shows pios wired for sequence detect function. commands, registers, and modes are capitalized for clarity. 1-wire is a registered trademark of dallas semiconductor. special features ? digital thermometer measures temperatures from -40c to +85c ? thermometer resolution is user-selectable from 9 to 12 bits ? unique 1-wire interface requires only one port pin for communication ? each device has a unique 64-bit factory- lasered registration number ? rom multidrop capability simplifies distributed temperature-sensing applications ? improved 1-wire interface with hysteresis and glitch filter ? user-definable nonv olatile (nv) alarm threshold settings/user bytes ? alarm search command to quickly identify devices whose temperature is outside of programmed limits ? standard and overdrive 1-wire speed ? two general-purpose programmable io (pio) pins ? chain function sharing the pio pins to detect physical sequence of devices in network ? operating range: 3.0v to 5.5v, -40c to +85c ? can be powered from data line ? 8-pin sop package ordering information part temp range package DS28EA00U+ -40 to +85c 8-pin sop DS28EA00U+t -40 to +85c tape & reel + denotes lead-free package. pin configuration 1 2 3 4 8 7 6 5 v dd piob pioa nc io nc nc gnd + 8 pin sop package outline drawing 21-0036 ds28ea00 1-wire digital thermomete r with sequence detect and pio www.maxim-ic.com
ds28ea00 1-wire digital thermometer with sequence detect and pio 2 of 29 absolute maximum ratings io voltage to gnd -0.5v, +6v io sink current 20ma maximum pioa or piob pin current 20ma maximum current through gnd pin 40ma operating temperature range -40c to +85c junction temperature +150c storage temperature range -55c to +125c soldering temperature see ipc/jedec j-std-020 stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of t he specifications is not implied. exposure to the absolute maximum rati ng conditions for extended peri ods may affect device. electrical characteristics (t a = -40c to +85c; see note 1) parameter symbol conditions min typ max units power supply supply voltage v dd (note 2) 3.0 5.5 v supply current (note 5) i dd v dd = 5.5v 1.5 ma standby current i dds v dd = 5.5v 1.5 a io pin general data local power 3.0 v dd 1-wire pullup voltage (note 2) v pup parasite power 3.0 5.5 v 1-wire pullup resistance r pup (notes 2, 3) 0.3 2.2 k input capacitance c io (notes 4, 5) 1000 pf input load current i l io pin at v pup 0.1 1.5 a high-to-low switching threshold v tl (notes 5, 6, 7) 0.46 v pup - 1.9v v parasite powered 0.5 input low voltage (notes 2, 8) v il v dd powered (note 5) 0.7 v low-to-high switching threshold (notes 5, 6, 9) v th parasite power 1.0 v pup - 1.1v v switching hysteresis (notes 5, 6, 10) v hy parasite power 0.21 1.7 v output low voltage (note 11) v ol at 4ma 0.4 v standard speed, r pup = 2.2k 5 overdrive speed, r pup = 2.2k 2 recovery time (notes 2, 12) t rec overdrive speed, directly prior to reset pulse; r pup = 2.2k 5 s standard speed 0.5 5.0 rising-edge hold-off time (notes 5, 13) t reh overdrive speed not applicable (0) s standard speed 65 timeslot duration (notes 2, 14) t slot overdrive speed 8 s io pin, 1-wire reset, presence detect cycle standard speed 480 640 reset low time (note 2) t rstl overdrive speed 48 80 s standard speed 15 60 presence-detect high time t pdh overdrive speed 2 6 s standard speed 1.125 8.1 presence-detect fall time (notes 5, 15) t fpd overdrive speed 0 1.3 s standard speed 60 240 presence-detect low time t pdl overdrive speed 8 24 s standard speed 68.1 75 presence-detect sample time (notes 2,16) t msp overdrive speed 7.3 10 s
ds28ea00 1-wire digital thermometer with sequence detect and pio 3 of 29 parameter symbol conditions min typ max units io pin, 1-wire write standard speed 60 120 write-0 low time (notes 2, 17) t w0l overdrive speed 6 16 s standard speed 5 15 write-1 low time (notes 2, 17) t w1l overdrive speed 1 2 s io pin, 1-wire read standard speed 5 15 - read low time (notes 2, 18) t rl overdrive speed 1 2 - s standard speed t rl + 15 read sample time (notes 2, 18) t msr overdrive speed t rl + 2 s pio pins input low voltage v ilp (note 2) 0.3 v input high voltage (note 2) v ihp v x = max(v pup , v dd ) vx-1.6 v input load current (note 19) i lp pin at gnd -1.1 a output low voltage (note 11) v olp at 4ma 0.4 v chain-on pullup impedance r co (note 5) 20 40 60 k eeprom programming current i prog (notes 5, 20) 1.5 ma programming time t prog (note 21) 10 ms at +25c 200k write/erase cycles (en- durance) (notes 22, 23) n cy -40c to +85c 50k ? data retention (notes 24, 25) t dr at +85c (worst case) 10 years temperature converter conversion current i conv (notes 5, 20) 1.5 ma 12-bit resolution (1/16c) 750 11-bit resolution (1/8c) 375 10-bit resolution (1/4c) 187.5 conversion time (note 26) t conv 9-bit resolution (1/2c) 93.75 ms -10c to +85c -0.5 +0.5 conversion error ? below -10c (note 5) -0.5 +2.0 c converter drift ? d (note 27) -0.2 +0.2 c note 1: specifications at t a = -40c are guaranteed by design only and not production-tested. note 2: system requirement. note 3: maximum allowable pullup resistance is a func tion of the number of 1-wire devices in the system and 1-wire recovery times. the specified value here applies to parasitically powered systems with only one device and with the minimum 1-wire recovery times. for more heavily loaded systems, local power or an acti ve pullup such as that found in the ds2482-x00, ds2480b, or ds2490 may be required. if longer t rec is used, higher r pup values may be tolerable. note 4: value is 25pf max. with local power. maximum val ue represents the internal parasite capacitance when v pup is first applied. if r pup = 2.2k , 2.5s after v pup has been applied the parasite capacitance will not affect normal communications. note 5: guaranteed by design, characterization, and/ or simulation only. not production tested. note 6: v tl , v th , and v hy are a function of the internal supply voltage, which is itself a function v dd , v pup , r pup , 1-wire timing, and capacitive loading on io. lower v dd , v pup , higher r pup , shorter t rec , and heavier capacitive loading a ll lead to lower values of v tl , v th , and v hy . note 7: voltage below which, during a falling edge on io, a logic '0' is detected. note 8: the voltage on io needs to be less than or equal to v ilmax at all times the master drives the line to a logic '0'. note 9: voltage above which, during a rising edge on io, a logic '1' is detected. note 10: after v th is crossed during a rising edge on io, the voltage on io has to drop by at least v hy to be detected as logic '0'. note 11: the i-v characteristic is linear for voltages less than 1v. note 12: applies to a single parasitically powered ds28ea00 attached to a 1-wire line. these values also apply to networks of multiple ds28ea00 with local supply . note 13: the earliest recognition of a negative edge is possible at t reh after v th has been reached on the preceding rising edge. note 14: defines maximum possible bit rate. equal to 1/(t w0l(min) + t rec(min) ). note 15: interval during the negative edge on io at the beginning of a presen ce-detect pulse between the time at which the voltage is 80% of v pup and the time at which the voltage is 20% of v pup . note 16: interval after t rstl during which a bus master is guaranteed to sample a l ogic '0' on io if there is a ds28ea00 present. minimum limit is t pdh(max) + t fpd(max) ; maximum limit is t pdh(min) + t pdl(min) . note 17: in figure 14 represents the time required for the pullup circuitry to pull the voltage on io up from v il to v th . the actual maximum duration for the master to pull the line low is t w1lmax + t f - and t w0lmax + t f - respectively.
ds28ea00 1-wire digital thermometer with sequence detect and pio 4 of 29 note 18: in figure 14 represents the time required for the pullup circuitry to pull the voltage on io up from v il to the input high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f note 19: this load current is caused by the internal weak pullup, which asserts a logic '1' to the piob and pioa pins. the logical state of piob must not change during the execution of the conditional read rom command. note 20: current drawn from io during eeprom programming or temperat ure conversion interval in par asite powered mode. the pullup circuit on io during the programming or temp erature conversion interval should be such that the voltage at io is greater than o r equal to v pup(min) . if v pup in the system is close to v pup(min) then a low impedance bypass of r pup , which can be activated during programming or temperature conversions may need to be added. the bypass must be activated within 10s from the beginning of the t prog or t conv interval, respectively. note 21: the t prog interval begins t rehmax after the trailing rising edge on io for the last time slot of the command byte for a valid copy scratchpad sequence. interval ends once the device's self-timed eeprom programming cycle is complete and the current drawn by the device has returned from i prog to i l (parasite power) or i dds (local power). note 22: write-cycle endurance is degraded as t a increases. note 23: not 100% production-tested; guaranteed by reliability monitor sampling. note 24: data retention is degraded as t a increases. note 25: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of th is production test to data shee t limit at operating temperature range is established by reliability testing. note 26: the t conv interval begins t rehmax after the trailing rising edge on io for the last time slot of the command byte for a valid convert temperature sequence. interval ends once the device's self-timed tem perature conversion cycle is complete and the current drawn by the device has returned from i conv to i l (parasite power) or i dds (local power). note 27: drift data is preliminary and based on a 1000-hour stress te st performed on another device with comparable design and fabricated in the same manufacturing process. this test was performed at greater than +85c with v dd = 5.5v. confirmed thermal drift results for this device are pending the completion of a new 1000-hour stress test. pin description pin name function 1 io 1-wire bus interface and parasitic power s upply. open-drain, requires external pullup resistor. 4 gnd ground supply 2, 3, 5 n.c. no connection 6 pioa (done\) open-drain pioa channel and chain output . for sequence detection, pioa must be connected to piob of the next device in the chain; leave open or tie to gnd for the last device in the chain. 7 piob (en\) open-drain piob channel and chain input . for sequence detection, piob of the first device in the chain must be tied to gnd. 8 v dd power supply pin. must be tied to gnd for operation in parasite power mode.
ds28ea00 1-wire digital thermometer with sequence detect and pio 5 of 29 overview the block diagram in figure 1 shows the relationships between the major function blocks of the ds28ea00. the device has three main data components: 1) 64-bit regist ration number, 2) 64-bit scratchpad, and 3) alarm and configuration registers. the 1-wire rom function control unit processes the rom function commands that allow the device to function in a networked environment. the devic e function control unit implements the device-specific control functions, such as read/write, temperature conver sion, setting the chain state for sequence detection, and pio access. the crc generator assists the master ve rifying data integrity when reading temperatures and memory data. in the sequence detect pr ocess, piob functions as an input, whil e pioa provides the connection to the next device. the power supply sensor allows the mast er to remotely read whether the ds28ea00 has local power available. figure 2 shows the hierarchical structur e of the 1-wire protocol. the bus mast er must first provide one of the eight rom function commands: 1) read rom, 2) match rom, 3) search rom, 4) conditional (?alarm?) search rom, 5) conditional read rom, 6) skip rom, 7) overdrive-sk ip rom or 8) overdrive-match rom. upon completion of an overdrive rom command byte execut ed at standard speed, the device en ters overdrive mode, where all subsequent communication occurs at a higher speed. t he protocol required for t hese rom function commands is described in figure 12. after a rom function command is successfully executed, the device-specific control functions become accessible and the master may provi de any one of the nine availabl e commands. the protocol for these control function commands is described in figure 10. all data is read and written least significant bit first. figure 1. ds28ea00 block diagram power supply sensor v dd internal v dd 64-bit registration # 1-wire rom function control io device function control 8-bit crc generator alarm and config registers 64-bit scratchpad temperature sensor pio a piob ( en\ ) ( done\ ) ( on \ ) r co
ds28ea00 1-wire digital thermometer with sequence detect and pio 6 of 29 64-bit registration number each ds28ea00 contains a unique registra tion number that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. see figure 3 for details. the 1-wire crc is generated using a polynomial gener ator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the dallas 1-wire cyclic redundancy check (crc) is available in application note 27 . the shift register bits are initialized to 0. then starting wi th the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then the 48-bit serial number is entered. after the last byte of the serial number has been entered, the shift register cont ains the crc value. shifting in the 8 bits of crc returns the sh ift register to all 0s. figure 2. hierachical struct ure for 1-wire protocol ds28ea00 available commands: command level: data field affected: 1-wire rom function commands (see figure 12) read rom match rom search rom conditional search rom conditional read rom skip rom overdrive skip overdrive match 64-bit reg. # 64-bit reg. # 64-bit reg. # 64-bit reg. #, temperature alarm registers, scratchpad 64-bit reg. #, piob pin state, chain state (none) 64-bit reg. #, od-flag 64-bit reg. #, od-flag device-specific control function commands (see figure 10) write scratchpad read scratchpad copy scratchpad convert temperature read power mode recall eeprom pio access read pio access write chain scratchpad scratchpad temperature alarm and configuration registers scratchpad, temperature alarm registers v dd pin voltage scratchpad, temperature alarm and configuration registers pio pins pio pins chain state, pioa pin state figure 3. 64-bit registration number msb lsb 8-bit crc code 48-bit serial number 8-bit family code (42h) msb lsb msb lsb msb lsb
ds28ea00 1-wire digital thermometer with sequence detect and pio 7 of 29 figure 4. 1-wire crc generator x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 8 + x 5 + x 4 + 1 1 st stage 2 nd stage 3 rd stage 4 th stage 6 th stage 5 th stage 7 th stage 8 th stage input data memory description the memory of the ds28ea00 is shown in figure 5. it consists of an 8-byte scr atchpad and 3 bytes of backup eeprom. the first two bytes form the temperature read out register, which is updated after a temperature conversion and is read-only. the next 3 bytes are user-w riteable; they contain the temperature high (th) and the temperature low (tl) alarm register and a configuration register. the remaining 3 bytes are ?reserved?. they power up with constant data and cannot be written by the user. the th, tl, and configuration register data in the scratchpad control the resolution of a tem perature conversion and decide whether a temperature is considered as ?alarming?. th, tl, and configuration can be copied to the eeprom to bec ome nonvolatile (nv). the scratchpad is automatically loaded with eeprom da ta when the ds28ea00 powers up. figure 5. memory map byte address scratchpad (power-up state) backup eeprom 0 temperature lsb (50h) n/a 1 temperature msb (05h) n/a 2 th register or user byte 1* <--- -----> th register or user byte 1 3 tl register or user byte 2* <--- -----> tl register or user byte 2 4 configuration register* <----- ---> configuration register 5 reserved (ffh) n/a 6 reserved (0ch) n/a 7 reserved (10h) n/a *power-up state depends on va lue(s) stored in eeprom. register detailed description temperature readout register addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 ls byte 1 s s s s s 2 6 2 5 2 4 ms byte
ds28ea00 1-wire digital thermometer with sequence detect and pio 8 of 29 the temperature reading is in c using a 16-bit sign- extended two?s complement format. table 1 shows examples of temperature and the corresponding data for 12-bit resolution. with two?s complement, the sign bit is set if the value is negative. if the device is configured for 12-bit reso lution, all bits in the ls byte are valid; for a reduced resolution, bit 0 (11 bit mode), bits 0 to 1 (10 bit mode), and bits 0 to 2 (9 bit mode) are undefined. table 1. temperature/ data relationship temperature digital output (binary) digital output (hex) +85c* 0000 0101 0101 0000 0550h +25.0625c 0000 0001 1001 0001 0191h +10.125c 0000 0000 1010 0010 00a2h +0.5c 0000 0000 0000 1000 0008h 0c 0000 0000 0000 0000 0000h -0.5c 1111 1111 1111 1000 fff8h -10.125c 1111 1111 0101 1110 ff5eh -25.0625c 1111 1110 0110 1111 fe6fh -40c 1111 1101 1000 0000 fd80h *the power-on reset value of the tem perature readout register is +85c. temperature alarm registers addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 high alarm (th) 3 s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 low alarm (tl) the result of a temperature conversion is automatically compared to the values in the alarm registers to determine whether an alarm condition exists. alarm thresholds are represented as two?s complement number. with 8 bits available for sign and value, alarm thresholds can be set in increments of 1c. an alarm condition exists if a temperature conversion results in a value that is either higher than or equal to the value stored in the th register or lower than or equal to the value stored in the tl register. if a te mperature alarm condition exists, the device will respond to the conditional search command. the alar m condition is cleared if a subsequent temperature conversion results in a temperature reading within the boundaries defined by the data in the th and tl registers. configuration register addr b7 b6 b5 b4 b3 b2 b1 b0 4 0 r1 r0 1 1 1 1 1 the functional assignments of the indi vidual bits are explained in the table below. bits 0 to 4 and bit 7 have no function; they cannot be changed by the user. as a fact ory default, the device operates in 12-bit resolution. bit description bit(s) definition r0, r1: temperature converter resolution b5, b6 these bits control the reso lution of the temperature converter. the codes are as follows: r1 r0 0 0 9 bits 0 1 10 bits 1 0 11 bits 1 1 12 bits
ds28ea00 1-wire digital thermometer with sequence detect and pio 9 of 29 pio structure each pio consists of an open-drain pulldown transistor and an input path to read the pin state. the transistor is controlled by the pio output latch, as shown in figure 6. the device function control unit connects the pios logically to the 1-wire interface. pioa has a pullup path to internal v dd to facilitate the seq uence detect function (see figure 1) in conjunction with the chain command; piob is truely an open-drain structure. the power-on default state of the pio output transistors is off; high-imp edance on-chip resistors (not shown in the graphic) pull the pio pins to internal v dd . figure 6. pio simplified logic diagram pio pin state pio pin pio out- put latch pio output latch state. q d q pio data pio clock clock chain function the chain function is a feature that allows the 1-wire master to discover the physical s equence of devices that are wired as a linear network (?chai n?). this is particularly convenient for de vices that are installed at equal spacing along a long cable, e.g., to measure temperatures at diffe rent locations inside a storage tower or tank. without chain function, the master needs a lookup table to corre late registration number to the physical location. the chain function requires two pins, an input (en\) to enable a device to respond during the discovery and an output (done\) to inform the next device in the chain that the discovery of its neighbor is done . the two general purpose ports of the ds28ea00 are re-used for the chai n function. piob functions as en\ input and pioa generates the done\ signal, which is connected to the en \ input of the next device, as shown in the typical operating circuit on page 1. the en\ input of the first device in the chain needs to be hardwired to gnd or logic ?0? must be applied for the duration of the sequence discovery proc ess. besides the two pins , the sequence discovery relies on the conditional read rom command. for the chain function and normal pio operation to coexis t, the ds28ea00 distinguishes three chain states, off, on, and done. the transition from one chain state to another is controlled through the chain command. table 2 summarizes the chain states and the specific behavior of the pio pins. table 2. chain states device behavior chain state piob (en\) pioa (done\ ) conditional read rom off (default) pio (high impedance) pio (high impedance) not recognized on en\ input pullup on recognized if en\ is ?0? done no function pulldown on (do\ logic ?0?) not recognized the power-on default chain state is off , where pioa and piob are solely controlled through the pio access read and write commands. in the chain on state pioa is pulled high to the device?s internal v dd supply through a ~40k resistor, applying a logic ?1? to the piob (en\) pi n of the next device. only in the on state does a ds28ea00 respond to the conditional read rom command, prov ided its en\ is at logic ?0?. after a device?s rom
ds28ea00 1-wire digital thermometer with sequence detect and pio 10 of 29 registration number is read, it is put into the chain done state, which enables the next device in the chain to respond to the conditional read rom command. at the beginning of the sequence discov ery process all devices are put into th e chain on state. as the discovery progresses, one device after another is transitioned into the done state until all devices are identified. finally, all devices are put into the chain off state, which releases the pios and restores th eir power-on default state. control function commands the control function flow chart (figure 10) describes the protocols necessary for measuring temperatures, accessing the memory and pios, and changing the chain stat e. examples on how to use these and other functions are included at the end of this document. the communic ation between master and ds28ea00 takes place either at standard speed (default, od = 0) or at overdrive speed (od = 1). if not explicitly set into the overdrive mode after power-up the ds28ea00 communi cates at standard speed. write scratchpad [4eh] this command allows the master to write 3 bytes of data to the scratchpad of the ds28 ea00. the first data byte is associated with the th register (byte address 2), the second byte is associated with the tl register (byte address 3), and the third byte is associated wi th the configuration regist er (byte address 4). data must be transmitted least significant bit first. all three bytes must be written before the master issues a reset, or the data may be corrupted. read scratchpad [beh] this command allows the master to read the contents of the scratchpad. the data transfer starts with the least significant bit of the temperature readout register at byte address 0 and continues through the remaining 7 bytes of the scratchpad. if the master continues reading, it gets a 9 th byte, which is an 8-bit crc of all the data in the scratchpad. this crc is generated by the ds28ea00 and uses the same polynomial function as is used with the rom registration number. the crc is transmitted in its true (non-inverted) form. the master may issue a reset to terminate the reading early if only part of the scratchpad data is needed. copy scratchpad [48h] this command copies the contents of the scratchpad byte add resses 2 to 4 (th, tl and configuration registers) to the back-up eeprom. if the device has no v dd power, the master must enable a strong pullup on the 1-wire bus for the duration of t progmax within 10s after this command is issued. if the device is powered through the v dd pin, the master may generate read time slots to monitor the copy proc ess. copy is completed when the master reads 1- bits instead of 0-bits. convert temperature [44h] this command initiates a temperature conversion. following the c onversion, the resulting thermal data is found in the temperature readout regi ster in the scratchpad and the ds28ea00 return s to its low-power idle state. if the device has no v dd power, the master must enable a strong pullup on the 1-wire bus for the duration of the applica- ble resolution-dependent t convmax within 10s after this command is issued. if the device is powered through the v dd pin, the master may generate read time slots to monito r the conversion process. t he conversion is completed when the master reads 1-bits instead of 0-bits. read power mode [b4h] for copy scratchpad and convert temperature the ma ster needs to know whether the ds28ea00 has v dd power available. the read power mode command is implemented to pr ovide the master with this information. after the command code, the master issues read time slots. if t he master reads 1?s, the device is powered through the v dd pin. if the device is powered through the 1-wire line, the ma ster will read 0?s. the power supply sensor samples the state of the v dd pin for every time slot that the ma ster generates after the command code.
ds28ea00 1-wire digital thermometer with sequence detect and pio 11 of 29 recall eeprom [b8h] this command recalls the th and tl alarm trigger values and configuratio n data from backup eeprom into their respective locations in the scratchpad. after having transmitted the command code, the master may issue read time slots to monitor the completion of the recall process. recall is completed when the master reads 1-bits instead of 0-bits. the recall occurs automatically at power -up, not requiring any activity by the master. pio access read [f5h] this command reads the pio logical status and reports it together with the state of the pio output latch in an endless loop. a pio access read can be terminated at any time with a 1-wire reset. pio access read can be executed in the chain on and chain done state. while the device is in chai n on or chain done state, the pio output latch states will always re ad out as 1s; the pio pin state may not be reported correctly. pio status bit assignment b7 b6 b5 b4 b3 b2 b1 b0 complement of b3 to b0 piob output latch state piob pin state pioa output latch state pioa pin state the state of both pio channels is sampled at the same ti me. the first sampling occurs during the last (most significant) bit of the command code f5h. the pio status is then reported to the bus master. while the master receives the last (most significant) bi t of the pio status byte, the next samp ling occurs and so on until the master generates a 1-wire reset. the sampling occurs with a delay of t reh +x from the rising edge of the ms bit of the previous byte, as shown in figure 7. the value of "x" is approximately 0.2s. figure 7. pio access read timing diagram io ms 2 bits of previous byte ls 2 bits of pio status byte v th sampling point t reh +x notes: 1 the "previous byte" could be the command code or the data byte resulting from the previous pio sample. 2 the sample point timing also applies to the pio acce ss write command, with the "previous byte" being the write confirmation byte (aah). pio access write [a5h] the pio access write command writes to the pio output la tches, which control the pulldown transistors of the pio channels. in an endless loop this command first writes new data to the pio and then reads back the pio status. this implicit read-after-write can be used by the master for status verification. a pio access write can be termi- nated at any time with a 1-wire reset. the pio access wri te command is ignored by the device while in chain on or chain done state. pio output data bit assignment b7 b6 b5 b4 b3 b2 b1 b0 x x x x x x piob pioa
ds28ea00 1-wire digital thermometer with sequence detect and pio 12 of 29 after the command code the master tran smits a pio output data byte that determines the new state of the pio output transistors. the first (least significant) bit is associat ed to pioa; the next bit affects piob. the other 6 bits of the new state byte do not have corresponding pio pins. thes e bits should always be transmitted as "1"s. to switch the output transistor on, the corresponding bit value is 0. to switch the out put transistor off (non-conducting) the bit must be 1. this way the bit transmitted as the new pi o output state arrives in its true form at the pio pin. to protect the transmission against data errors, the master must repeat the pio output data byte in its inverted form. only if the transmission was error-free will the pio status change. the actual pio transition to the new state occurs with a delay of t reh + x from the rising edge of the ms bit of the inve rted pio byte, as shown in figure 8. the value of "x" is approximately 0.2s. to inform the master about the successful communica tion of the pio byte, the ds28ea00 transmits a confirmation byte with the data patte rn aah. while the ms bit of the confirmation byte is transmitted, the ds28ea00 samples the state of the pio pins , as shown in figure 7, and sends it to the master. the master can either continue writing more data to the pio or issue a 1-wire reset to end the command. figure 8. pio access write timing diagram io pio ms 2 bits of inverted pio output data byte ls 2 bits of confir- mation byte (aah) v th t reh +x chain command [99h] this command allows the master to put the ds28ea00 into one of the three chain states, as shown in figure 9. the device powers up in the chain off state. to trans ition a ds28ea00 from one state to another, the master must send a suitable chain control byte after the chai n command code. only the codes 3ch, 5ah and 96h (true form) are valid, assigned to off, on, and done , in this sequence. this control by te is first transmitted in its true form and then in its inverted form. if the chain state chan ge was successful, the master receives aah confirmation bytes. if the change was not successful (control byte transmission error, inva lid control byte) the master will read 00h bytes instead. figure 9. chain state transition diagram chain on chain off or por chain done these transitions are permissible, but do not occur during normal operation. off power-on reset (por) chain done chain on on done
ds28ea00 1-wire digital thermometer with sequence detect and pio 13 of 29 figure 10-1. control function flow chart from figure 10 2 nd part to figure 10 2 nd part y n beh read scratch- pad? y n 4eh write scratch- pad? to rom functions flow chart (figure 12) master tx data byte to scratchpad ds28ea00 sets byte address = 2 ds28ea00 incre- ments byte address n y byte address = 4? n y master tx reset? y n master tx reset? master rx byte from scratchpad ds28ea00 sets byte address = 0 ds28ea00 incre- ments byte address n y byte address = 7? n y master tx reset? master rx 8-bit crc of data n y master tx reset? master rx ?1s? bus master tx control function command from rom functions flow chart (figure 12)
ds28ea00 1-wire digital thermometer with sequence detect and pio 14 of 29 figure 10-2. control functi on flow char t (continued) from figure 10 3 rd part to figure 10 3 rd part to figure 10 1 st part from figure 10 1 st part y n 48h copy scratch- pad? y n v dd powered? ds28ea00 starts copy to eeprom n y copy completed? master rx ?0s? master activates strong pull-up for t prog ds28ea00 copies scratchpad data to eeprom master deactivates strong pull-up n y master tx reset? master rx ?1s? y n 44h convert tempera- ture y n v dd powered? ds28ea00 starts temperature conversion n y conversion completed? master rx ?0s? master activates strong pull-up for t conv ds28ea00 converts temperature master deactivates strong pull-up n y master tx reset? master rx ?1s? master decision . the master needs to know whether v dd power is available.
ds28ea00 1-wire digital thermometer with sequence detect and pio 15 of 29 figure 10-3. control functi on flow chart (continued) to figure 10 4 th part from figure 10 2 nd part to figure 10 2 nd part master rx ?0s? y n b4h read power mode? y n v dd powered? master rx ?1s? n y master tx reset? y n b8h recall eeprom? n y master tx reset? master rx ?1s? ds28ea00 starts recall eeprom to scratchpad n y recall completed? master rx ?0s? master rx ?1s? from figure 10 4 th part
ds28ea00 1-wire digital thermometer with sequence detect and pio 16 of 29 figure 10-4. control function flow chart (continued) to figure 10 5 th part to figure 10 3 rd part from figure 10 3 rd part y f5h pio access read? y n master tx reset? bus master rx pio pin status y n a5h pio access write? bus master tx new pio output data byte bus master tx inverted new pio output data byte transmission ok? ds28ea00 updates pio bus master rx confirmation aah ds28ea00 samples pio pin bus master rx pio pin status y n master tx reset? n y bus master rx ?1?s y n master tx reset? note 1) see the command description for the exact timing of the pio pin sampling and updating. n y ds28ea00 samples pio pin 1 ) 1 ) 1 ) from figure 10 5 th part
ds28ea00 1-wire digital thermometer with sequence detect and pio 17 of 29 figure 10-5. control functi on flow chart (continued) from figure 10 4 th part n y master tx reset? master rx ?1s? y n 99h chain command? master tx inverted chain control byte master tx chain control byte ds28ea00 up- dates chain state y n control byte valid? n y transmission error? y n master tx reset? master rx con- firmation code aah y n master tx reset? master rx error code 00h valid chain control byte codes: 3ch off 5ah on 96h done error defined as: repeated control byte not equal to inverted control byte to figure 10 4 th part y n master tx reset? master rx inverted chain control byte
ds28ea00 1-wire digital thermometer with sequence detect and pio 18 of 29 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. in all instances the ds28ea00 is a slave device. the bus master is typica lly a microcontroller. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequen ce, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transactions in terms of the bus state during specif ic time slots, which are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1-wire bus has only a single line by definition; it is impo rtant that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attach ed to the 1-wire bus must have open-drain or tri-state outputs. the 1-wire port of the ds28ea00 is open drain with an internal ci rcuit equivalent to that shown in figure 11. a multidrop bus consists of a 1-wire bus with multip le slaves attached. the ds28ea00 supports both a standard and overdrive communication speed of 15.3kbps (max) and 125k bps (max), respectively. note that legacy 1-wire products support a standard communication speed of 16. 3kbps and overdrive of 142kbp s. the slightly reduced rates for the ds28ea00 are a result of additional recovery ti mes, which in turn were driven by a 1-wire physical interface enhancement to improve noise immunity. the va lue of the pullup resistor primarily depends on the network size and load conditions. the ds 28ea00 requires a pullup resistor of 2.2k (max) at any speed. the idle state for the 1-wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16s (overdrive speed) or more than 120s (standard speed), one or more devices on the bus may be reset. figure 11. hardware configuration open-drain port pin rx = receive tx = transmit 100 mosfet v pup rx tx tx rx data i l bus master ds28ea00 1-wire port r pup transaction sequence the protocol for accessing the ds28ea00 th rough the 1-wire port is as follows: ? initialization ? rom function command ? control function command ? transaction/data initialization all transactions on the 1-wire bus begin with an initializat ion sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presen ce pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds28ea00 is on t he bus and is ready to operate. for more details, see the 1-wire signaling section.
ds28ea00 1-wire digital thermometer with sequence detect and pio 19 of 29 1-wire rom func tion commands once the bus master has detected a presence, it can issue one of the eight rom function commands that the ds28ea00 supports. all rom function commands are 8 bits long. a list of these commands follows (refer to the flow chart in figure 12). read rom [33h] this command allows the bus master to read the ds28ea 00?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired- and result). the resultant family code and 48-bit se rial number result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom seq uence, allows the bus master to address a specific ds28ea00 on a multidrop bus. only the ds28ea00 that exactly matches the 64-bit rom sequence responds to the following control function command. all other slaves wait for a reset pulse. this command can be used with a single or multiple devices on the bus. search rom [f0h] when a system is initially brought up, the bus master might not know the nu mber of devices on the 1-wire bus or their registration numbers. by taking advantage of the wired-and property of the bus, the master can use a process of elimination to identify the registration number s of all slave devices. for each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the sear ch outputs the true value of its regist ration number bit. on the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. on the third slot, the master writes the true value of the bit to be selected. all slave devic es that do not match the bit written by the master stop participating in the search. if both of the read bits are zero, the master knows that slave devices exist with both states of the bit. by choosing whic h state to write, the bus master branches in the rom code tree. after one complete pass, the bus master know s the registration number of a single device. additional passes identify the registration numbers of the remaining devices. refer to application note 187: 1-wire search algorithm for a detailed discussion, including an example. the search rom command does not reveal any information about the location of a device in a networ k. if multiple ds28ea00 are wired as a linear network (?chain?), the device location can be detected using conditional read rom in conjunction with the chain function. conditional se arch rom [ech] the conditional search rom command operates similarly to the search rom command except that only those devices, which fulfill certain conditions, participates in the search. this function provides an efficient means for the bus master to identify devices on a mult idrop system that have to signal an im portant event. after each pass of the conditional search that successfully determined the 64-bit rom code for a specific device on the multidrop bus, that particular device can be individua lly accessed as if a match rom had been issued, since all other devices will have dropped out of the search process and will be waiti ng for a reset pulse. the ds28ea00 will respond to the conditional search if a temperature alar m condition exists. for more details see temperature alarm registers . conditional read rom [0fh] this command is used in conjunction with the chain function to detect the physical sequence of devices in a linear network (?chain?). a ds28ea00 responds to conditional read rom if two conditions are met: a) the device is in chain on state, and b) the en\ input (piob) is at logic ?0 ?. this condition is met by exactly one device during the sequence discovery process. upon rece iving the conditional read rom command, this particular device transmits its 64-bit registration numbera device in chain on state, but with a logic ?1? level at en\ does not respond to conditional read rom. see sequence discovery procedure for more details on the use of conditional read rom and the chain command.
ds28ea00 1-wire digital thermometer with sequence detect and pio 20 of 29 skip rom [cch] this command can save time in a single-drop bus system by allowing the bus master to access the control functions without providing the 64-bit rom code. if more than one slave is present on the bus and, for example, a read command is issued following the skip rom command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldow ns produce a wired-and result). overdrive skip rom [3ch] on a single-drop bus this command can save time by a llowing the bus master to access the control functions without providing the 64-bit rom code. unlike the norm al skip rom command, the overdrive skip rom sets the ds28ea00 in the overdrive mode (od = 1). all communicati on following this command has to occur at overdrive speed until a reset pulse of minimum 480s duration resets all devices on the bus to standard speed (od = 0). when issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. to subsequently address a specific over drive-supporting device, a reset pulse at overdrive speed has to be issued followed by a match rom or search rom command sequence . this speeds up the time for the search process. if more than one slave supporting overdr ive is present on the bus and the overdrive skip rom command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-and result). overdrive match rom [69h] the overdrive match rom command followed by a 64-bit ro m sequence transmitted at overdrive speed allows the bus master to address a specific ds28ea00 on a multid rop bus and to simultaneously set it in overdrive mode. only the ds28ea00 that exactly matches the 64-bit ro m sequence responds to the subsequent control function command. slaves already in overdrive mode from a prev ious overdrive skip or successful overdrive match command remain in overdrive mode. all overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480s duration. the overdrive match rom comm and can be used with a single or multiple devices on the bus.
ds28ea00 1-wire digital thermometer with sequence detect and pio 21 of 29 figure 12-1. rom funt ions flow chart from figure 12 2 nd part to control functions flow chart (figure 10) master tx bit 0 master tx bit 63 master tx bit 1 ds28ea00 tx crc byte ds28ea00 tx serial number (6 bytes) ds28ea00 tx family code (1 byte) bit 0 match? y n bit 1 match? y n bit 63 match? y n ds28ea00 tx bit 0 ds28ea00 tx bit 0 master tx bit 0 ds28ea00 tx bit 1 ds28ea00 tx bit 1 master tx bit 1 ds28ea00 tx bit 63 ds28ea00 tx bit 63 master tx bit 63 bit 0 match? y n bit 1 match? y n bit 63 match? y n to figure 12 2 nd part y y y y n f0h search rom command? n 55h match rom command? n ech cond. search command? n 33h read rom command? to figure 12 2 nd part from control functions flow chart (figure 10) bus master tx rom function command ds28ea00 tx presence pulse od reset pulse? n y od = 0 bus master tx reset pulse from figure 12, 2 n d par t temp. alarm? y n ds28ea00 tx bit 0 ds28ea00 tx bit 0 master tx bit 0 ds28ea00 tx bit 1 ds28ea00 tx bit 1 master tx bit 1 ds28ea00 tx bit 63 ds28ea00 tx bit 63 master tx bit 63 bit 0 match? y n bit 1 match? y n bit 63 match? y n
ds28ea00 1-wire digital thermometer with sequence detect and pio 22 of 29 figure 12-2. rom fu nctions flow chart y n y n n n od = 1 master tx bit 0 master tx bit 63 master tx bit 1 bit 0 match? bit 1 match? bit 63 match? y y 69h od match rom? od = 1 master tx reset ? y n y n 3ch od skip rom? from figure 12 1 st part from figure 12 1 st part to figure 12, 1 s t part y n cch skip rom cmnd.? to figure 12 1 st part y n 0fh cond. read rom? chain = on? y n en\ = low? y n ds28ea00 tx crc byte ds28ea00 tx serial number (6 bytes) ds28ea00 tx family code (1 byte) master tx reset? n y od = 0 od = 0 od = 0 1 ) 1) the od flag remains at 1 if the device was already at overdrive speed before the overdrive match rom command was issued. 1 ) 1 )
ds28ea00 1-wire digital thermometer with sequence detect and pio 23 of 29 1-wire signaling the ds28ea00 requires strict protocols to ensure data integrity. the protocol co nsists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. except for the presence pulse, the bus master initiates all fa lling edges. the ds28ea00 can communicate at two different speeds, standard speed, and overdrive speed. if not explicitly set into the overdrive mode, the ds28ea00 communicates at standard speed. while in overdriv e mode the fast timing applies to all waveforms. to get from idle to active, the voltage on the 1-wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v ilmax past the threshold v th . the time it takes for the voltage to make this rise is seen in figure 13 as ' ' and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1-wire network attached. the voltage v ilmax is relevant for the ds28ea00 when determining a logical level, not triggering any events. figure 13 shows the initialization sequence required to begin any communication with the ds28ea00. a reset pulse followed by a presence pulse indicates the ds28ea 00 is ready to receive data, given the correct rom and control function command. if the bus master uses slew-rat e control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. a t rstl duration of 480s or longer exit s the overdrive mode, returning the device to standard speed. if the ds 28ea00 is in overdrive mode and t rstl is no longer than 80s, the device remains in overdrive mode. if the device is in overdrive mode and t rstl is between 80s and 480s, the device will reset, but the communication speed is undetermined. figure 13. initialization proced ure ?reset and presence pulses? resistor master ds28ea00 t rstl t pdl t rsth t pdh master tx ?reset pulse? master rx ?presence pulse? v pup v ihmaster v th v tl v ilma x 0 v after the bus master has released the line it goes into receive mode. now the 1-wire bus is pulled to v pup through the pullup resistor, or in case of a ds2482-x00 or ds2480b driver, by active circuitry. when the threshold v th is crossed, the ds28ea00 waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the master must test the logical state of the 1-wire line at t msp . the t rsth window must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the ds28ea00 is ready for data communication. in a mixed population network, t rsth should be extended to minimum 480s at standard speed and 48s at overdrive speed to accommodate other 1-wire devices. read/write time slots data communication with the ds28ea00 takes place in time slots, which carry a single bit each. write-time slots transport data from bus master to slav e. read-time slots transfer data from slave to master. figure 14 illustrates the definitions of the writ e- and read-time slots. all communication begins with the master pulling the data lin e low. as the voltage on the 1-wire line falls below the threshold v tl , the ds28ea00 starts its internal timing generato r that determines when the data line is sampled during a write-time slot and how long data is valid during a read-time slot.
ds28ea00 1-wire digital thermometer with sequence detect and pio 24 of 29 master-to-slave for a write-one time slot, the voltage on the data line must have crossed the v th threshold before the write-one low time t w1lmax is expired. for a write-zero time slot, the voltage on the data line must stay below the v th threshold until the write-zero low time t w0lmin is expired. for the most reliabl e communication, the voltage on the data line should not exceed v ilmax during the entire t w0l or t w1l window. after the v th threshold has been crossed, the ds28ea00 needs a recovery time t rec before it is ready for the next time slot. figure 14. read/writ e timing diagram write-one time slot resistor master v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l write-zero time slot resistor master t rec v pup v ihmaster v th v tl v ilma x 0v t f t slot t w0l read-data time slot resistor master ds28ea00 t rec v pup v ihmaster v th v tl v ilma x 0v master sampling window t f t slot t rl t msr slave-to-master a read-data time slot begins like a write-one time slot. the voltage on the data line must remain below v tl until the read low time t rl is expired. during the t rl window, when responding with a 0, the ds28ea00 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds28ea00 does not hold the data li ne low at all, and the voltage starts rising as soon as t rl is over.
ds28ea00 1-wire digital thermometer with sequence detect and pio 25 of 29 the sum of t rl + (rise time) on one side and the internal timi ng generator of the ds28ea00 on the other side define the master sampling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for the most reliable communication, t rl should be as short as permissible, and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds28ea00 to get ready for the next time slot. note that t rec specified herein applies only to a single ds28ea00 attach ed to a 1-wire line. for multidevice configurations, t rec needs to be extended to accommodate the additional 1-wire de vice input capacitance. alternatively, an interface that performs active pullup during the 1-wire recovery time such as the ds2482-x00 or ds2480b 1-wire line drivers can be used. improved network behavior (switchpoint hysteresis) in a 1-wire environment, line termination is possible onl y during transients controlled by the bus master (1-wire driver). 1-wire networks, therefore, are susceptible to noise of vari ous origins. depending on the physical size and topology of the network, reflections from end points and br anch points can add up, or cancel each other to some extent. such reflections are visible as glitches or ringi ng on the 1-wire communication line. noise coupled onto the 1-wire line from external sources can also result in signal glitching. a glitch dur ing the rising edge of a time slot can cause a slave device to lose synchronization with the mast er and, consequently, result in a search rom command coming to a dead end or cause a device-specific functi on command to abort. for better performance in network applications, the ds28ea00 uses a new 1-wire front end, whic h makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave device itself.. the 1-wire front end of the ds28ea00 differs from trad itional slave devices in four characteristics. 1) the falling edge of the presence pulse has a controlled slew rate. this provides a better match to the line impedance than a digitally switched transistor, converting the high frequency ringing known from traditional devices into a smoother low-bandwidth transition. the slew rate control is specified by the parameter t fpd , which has different values for standard and overdrive speed. 2) there is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot. this reduces the sensitivity to high-frequency noise. this additional filtering does not apply at overdrive speed. 3) there is a hysteresis at the low-to-high switching threshold v th . if a negative glitch crosses v th but does not go below v th - v hy , it will not be recognized (figure 15, case a). the hysteresis is effective at any 1-wire speed. 4) there is a time window specified by the rising edge hold-off time t reh during which glitches are ignored, even if they extend below v th - v hy threshold (figure 15, case b, t gl < t reh ). deep voltage droops or glitches that appear late after crossing the v th threshold and extend beyond the t reh window cannot be filtered out and are taken as the beginning of a new time slot (figure 15, case c, t gl t reh ). devices that have the parameters v hy , and t reh specified in their electrical char acteristics use the improved 1-wire front end. figure 15. noise su ppression scheme v pup v th v hy 0v t reh t gl t reh t gl case a case c case b
ds28ea00 1-wire digital thermometer with sequence detect and pio 26 of 29 sequence discovery procedure precondition : the piob pin (en\) of the first dev ice in the chain is at logic 0. the pioa pin (done\) of the first device connects to the piob of the second device in the chain, etc., as shown in figure 16. the 1-wire master detects the physical sequence of the devices in the chain by performing the following procedure: starting condition : the master issues a skip rom command followed by a chain on command, which puts all devices in the chain on state. the pullup through r co of the pioa pin charges the pioa/piob connections to logic ?1? level at all devices except for the first device in t he chain. if a local vdd supply is not available, the master needs to activate a low-impedance bypass to the 1-wire pull up resistor immediately after the inverted chain control byte until the pioa/piob connections have reache d a voltage equivalent to the logic ?1? level. first cycle : the master sends a conditional read rom command, which causes the first device in the chain to respond with its 64-bit registration number. the master memorizes the registration number and the fact that this is the first device in the chai n. next the master transmits a chain done command. through the pioa pin of the just discovered device, this asserts logic 0 at the piob pin of the second device in the chain and also prevents the just discovered device from responding again. second cycle : the master sends a conditional read rom command. since ds28ea00 #2 is the only device in the chain with a low level at piob it responds with its registration number. the master stores the registration number with the sequence number of 2. device #1 cannot respond since it is in chain done state. next the master transmits a chain done command. additional cycles : to identify the registration num bers of the remaining devices an d their physical sequence, the master repeats the steps of conditional read rom , and chain done . if there is no response to conditional read rom, all devices in the chain are identified. ending condition at the end of the discovery process all devices in the c hain are in the chain done st ate. the master should end the sequence discovery by issuing a skip rom command followed by a chain off command. this puts all the devices into the chain off state, and transfers control of the piob and pioa pins to the pio access read and write function commands. figure 16. ds28ea00 wi red for sequence discover y (?chain function?) * * v dd 1-wire master px. y (micro- controller) #1 #2 #3 v dd io ds28ea00 piob pioa gnd v dd io ds28ea00 piob pioa gnd v dd io ds28ea00 piob pioa gnd * capacitance of the cabling between adjacent devices in the chain.
ds28ea00 1-wire digital thermometer with sequence detect and pio 27 of 29 command-specific 1-wire co mmunication pr otocol?legend symbol description rst 1-wire reset pulse generated by master. pd 1-wire presence pulse generated by slave. select command and data to satisfy the rom function protocol. skipr rom function command "skip rom". cdrr rom function command "conditional read rom". wsp command "write scratchpad". rsp command "read scratchpad". cpsp command "copy scratchpad". ctemp command "convert temperature". rpm command "read power mode". rcle command "recall eeprom". pior command "pio access read". piow command "pio access write". chain command "chain". transfer of n bytes. crc transfer of a crc byte transfer of a specific byte value ?xx? (hexadecimal notation) 00 loop indefinite loop where the master reads 00 bytes. ff loop indefinite loop where the master reads ff bytes. aa loop indefinite loop where the master reads aa bytes. xx loop indefinite loop where the slave trans mits the inverted invalid control byte. conversion a temperature conversion takes place; activi ty on the 1-wire bus is permitted only with local v dd supply. programming data transfer to backup eeprom; activity on t he 1-wire bus is permitted only with local v dd supply. command-specific 1-wi re communication prot ocol?color codes master to slave slave to master programming conversion write scratchpad rst pd select wsp <3 bytes> rst pd read scratchpad rst pd select rsp <8 bytes> crc ff loop
ds28ea00 1-wire digital thermometer with sequence detect and pio 28 of 29 copy scratchpad (parasite powered) rst pd select cps wait t progmax ff loop copy scratchpad (local v dd powered) rst pd select cps <00h> ff loop convert temperature (parasite powered) rst pd select ctemp wait t convmax ff loop convert temperature (local v dd powered) rst pd select ctemp <00h> ff loop read power mode (parasite powered) rst pd select rpm <00h> read power mode (local v dd powered) rst pd select rpm recall eeprom rst pd select rcle <00h> ff loop pio access read rst pd select pior the master reads 00h bytes until t he write cycle is completed. the master reads 00h bytes until the conversion is completed. during the wait, the master should activate a low- impedance bypass to the 1-wire pullup resistor. during the wait, the master should activate a low- impedance bypass to the 1-wire pullup resistor. the master reads 00h bytes unt il the recall is completed. continues until master sends reset pulse see the command description for behavior if the device is in chain on or chain done state.
ds28ea00 1-wire digital thermometer with sequence detect and pio 29 of 29 pio access write (success) rst pd select piow pio access write ( invalid data byte ) rst pd select piow ff loop the pio access write command is ignored by the de vice while in chain on or chain done state. change chain state (success) rst pd select chain aa loop change chain state ( transmission error ) rst pd select chain < byte inverted previous byte> 00 loop change chain state ( invalid control byte ) rst pd select chain xx loop sequence discovery example rst pd skipr chain <5ah> wait for chain to charge rst pd cdrr chain <96h> <69h> rst pd cdrr chain <96h> <69h> rst pd cdrr <8 bytes ffh> rst pd skipr chain <3ch> for the sequence discovery to function properly, the lo gic state at piob (en\) must not change during the transmission of the conditional read rom command code, and, if the device responds, mu st stay at logic 0 until the entire 64-bit registration number is transmitted. loop until master sends reset pulse identify the first device and put it into chain done state. identify the next device and put it into chain done state. repeat this sequence until no device responds. no response, all devices have been discovered. put all devices into chain off state. put all devices into chain on state.

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